As a digital modulation system used for wireless communication in recent years such as a cellular phone and a wireless LAN (Local Area Network), modulation scheme such as QPSK and multilevel QAM are employed. QPSK is an abbreviation of Quadrature Phase Shift Keying, and QAM is an abbreviation of Quadrature Amplitude Modulation.
In these modulation schemes, generally, signals locus forms amplitude modulation when symbol transitions occur. Accordingly, the amplitude (envelope) of a modulation signal superimposed on a carrier signal of a microwave bandwidth varies over time. The ratio of the peak power to the average power of the modulation signal is referred to as PAPR (Peak-to-Average Power Ratio).
When a signal having a large PAPR is amplified, a power supply device needs to supply sufficiently large power to an amplifier so as to prevent the waveform from being distorted with peak power in order to secure high linearity.
In other words, the amplifier needs to be operated in a large back-off power region that is sufficiently lower than the saturated output power restricted by the power supply voltage.
Generally, because linear amplifiers operating in class A or class B have maximum power efficiency nearly at the saturated output power, if the linear amplifiers are operated in the large back-off region, their average power efficiency lowers.
In an orthogonal frequency division multiplex (OFDM) system using a multi carrier adopted in the next-generation mobile phones, wireless LANs and digital television broadcasts, the PAPR thereof tends to increase. Accordingly, the average efficiency of the amplifier further lowers. Note that OFDM is an abbreviation of Orthogonal Frequency Division Multiplexing.
Therefore, an amplifier has a characteristic of high power efficiency in the large back off power region is desired.
As a system that amplifies a signal in the large back-off region and with wide dynamic range and high efficiency, a power amplification device of a digital amplitude modulation system is disclosed in Patent Document 1, for example. FIG. 10 is a diagram showing a configuration of a power amplification device disclosed in Patent Document 1. As shown in FIG. 10, an amplitude signal 1050 is converted by a digitizer 1005 (A/D (Analog/Digital) converter) into n-bit digital signals 1061, 1062 . . . and 106n. The converted digital signals are inputted to n class D switching amplifiers 1011 and 1012 . . . and 101n. The class D switching amplifier amplifies a carrier signal 1052 from a RF source 1010 based on a digital signal. When logic of the digital signal which is an output of the digitizer 1005 is in High, the class D switching amplifier outputs a signal amplified by the class D switching amplifier to a power combiner 1002. When logic of the digital signal which is an output of the digitizer 1005 is in Low, an output of the class D switching amplifier is grounded.
The power combiner 1002 includes transformers 1021, 1022 . . . and 102n connected in series, and adds the output voltages of the class D switching amplifiers 1011, 1012 . . . and 101n. The voltage added signal is supplied to a load.
A block diagram of a class D switching amplifier of full bridge type which is an example of the class D switching amplifier is shown in FIG. 3. Two FETs (Field Effect Transistors) 1a and 1b and two FETs 1c and 1d which are stacked for connection are connected in parallel. One terminal of the two FETs is grounded, and the other terminal thereof is connected to a common power supply VDD.
By inputting a carrier signal 52 (S1) and an opposite phase signal (S2) thereof as shown in FIG. 3, when S1 is in High and S2 is in Low, the power supply voltage VDD appears in an output. When S1 is in Low and S2 is in High, the polarity of the output reverses, and −VDD appears. This operation is repeated and the inputted carrier signal is amplified to a signal of 2×VDD by the voltage magnitude. At that time, because the respective FETs are performing switching operation and an overlap does not occur in waveforms of current and voltage, power loss is not generated in the FETs, and amplifying with very high efficiency.
In the full bridge type class D switching amplifier shown in FIG. 3, when inputs S1 and S2 of low side FETs 1b and 1d are set to in High, respectively, and inputs S1 and S2 of high side FETs 1a and 1c are set to in Low, respectively, a voltage does not generate in an output, and the output will be in a grounding state. For example, this operation can be realized by controlling the switches 111-114 of FIG. 3.
FIG. 10 is an example in which the full bridge type class D switching amplifier shown in FIG. 3 is applied as an amplifier of a digital amplitude modulation system amplifier. When digital signals 1061, 1062 . . . and 106n are High, a carrier signal and an opposite phase signal thereof are inputted to S1 and S2 respectively. On the other hand, when digital signals 1061, 1062 . . . and 106n are Low, an output will be in the grounding state by controlling the switches 111-114. By performing voltage addition of the output with transformers 1021-102n of FIG. 10, a carrier signal to which amplitude modulation is performed can be amplified with high efficiency is possible, and can be outputted to a load.
An amplifier of a digital amplitude modulation system of such a system is utilized in a medium wave radio transmitter, and high efficiency beyond 80% is realized.
However, when a digital modulation system amplifier shown in FIG. 10 is applied to a high frequency equal to or greater than a VHF (Very High Frequency) band, two problems arise.
The first problem is caused by parasitic capacitance Cp in the FET which composes the class D switching amplifier shown in FIG. 3. That is, when the switching frequency f becomes high, power loss of the magnitude Cp·V2·f (V is voltage magnitude applied to the FET) will generate. In other words, because the magnitude of the power loss is proportional to the frequency f, when the frequency f becomes high, power loss cannot be ignored any more, and high power efficiency cannot be maintained.
The second problem is loss in transformers 1021, 1022 . . . and 102n which perform voltage addition as a power combiner. This loss cannot also be ignored any more in a high frequency domain. In particular, when a handled power is large like a base station of a mobile phone and a broadcasting station, it is difficult to realize a low-loss transformer in a high frequency domain due to the nature of a transformer.
A method to solve this problem is disclosed by patent document 2 for example. FIG. 11 is a diagram of a configuration disclosed by patent document 2.
In this system, as shown in FIG. 11, a modulated analog signal generated by a modulation signal generator 1108 is inputted to an A/D converter 1105, and is converted into a digital modulation signal. After that, the digital modulation signal is inputted to an on/off controller 1106 and converted into a control signal for turning ON/OFF (switching) four switches SW1-SW4.
Here, an example in case there are four switches SW1-SW4 is shown. There are four switches because the four switches correspond to 4 bits which are the quantifying bit numbers of the output digital signal of the A/D converter 1105.
The above-mentioned control signal switches the switches SW1-SW4 in order to correspond to respective bits. The switches SW1-SW4 receive carriers generated by a carrier generator 1110 as input signals, and input the input carriers to the power amplifiers PA1-PA4, corresponding to a period currently controlled by ON.
The power amplifiers PA1-PA4 have weighted output levels, respectively for correspondence in each bit of the 4-bit digital signal.
For example, the power amplifier PA1 has an amplification degree proportional to 23 corresponding to a most significant bit (MSB) of the 4-bit digital signal. Similarly, the power amplifiers PA2, PA3 and PA4 have an amplification degree proportional to 22, 21 and 20, respectively.
Power combining of respective output signals of the power amplifiers PA1-PA4 is performed by power combiners 1121, 1122 and 1123 provided corresponding thereto. The configuration of the power combiners 1121, 1122 and 1123 are common. That is, the power combiners 1121, 1122 and 1123 include two 3 dB couplers, a variable phase shifter and a 90° phase shifter. A diagram illustrating operation of the 3 dB coupler is shown in FIG. 8. When a signal with which 90° phase shifted in an equal amplitude (for example, magnitude is set as “1”) is inputted to the 3 dB coupler, the combined power (magnitude “2”) appears in an output terminal, and a power does not occur in a dummy resistor connected to an isolation terminal (magnitude “0”). That is, the 3 dB coupler can combine the power without power loss.
Next, operation of a power combiner shown in FIG. 11 is described in an example of the power combiner 1121.
According to the arbitrary bit state, a signal of the different amplitude is generally inputted to the power combiner 1121. In this case, two outputs which appear from the first 3 dB coupler M1 are equal in the intensity of the voltage vector but different in the phase. When the phases of these two signals are set to x° and y°, a voltage signal whose phase is arranged to −45° in an equal amplitude is obtained by rotating the phases only by +{(y°−x°)/2} and −){(y°−x°)/2} using phase shifters PH11 and PH12 respectively.
Two signals whose phases are shifted by 90° each other in an equal amplitude can be obtained by delaying the phase of one of the signals by 90° with the phase shifter SH1. By inputting the two signals to the second 3 dB coupler M2, the combined power appears in an output terminal, and a power does not occur in a dummy resistor R1. That is, the two signals can be combined without loss.
By performing the same operation by power combiners 1122 and 1123, and connecting the power combiners 1122 and 1123 in series, power according to the arbitrary bit state can be combined without loss.
Phase shifting of the phases of the carrier signals inputted into SW1-SW4 is performed in advance to −270°, −135°, 0° and 0°, respectively by phase devices φ1, φ2, φ3 and φ4 in order to arrange the phases of the carrier signals. After that, each of carrier signals are inputted to the amplifiers PA1, PA2, PA3 and PA4, respectively.
An advantage of this system compared with the system of FIG. 10 is that the system does not need to use a class D switching amplifier like FIG. 3, and high frequency operation becomes possible by using amplifiers of class A, class B or class C which operates as a current source. Because each of the power combiners connected to respective power amplifiers are insulated, when the amplifiers are in the on/off state, the output impedance does not need to be 0. That is, the amplifier does not need to be a voltage source. Because the amplifiers of class A, class B, or class C do not have a problem of power loss in a high frequency region as described above, high frequency operation becomes possible by using these amplifiers.
High frequency operation is also possible for a 3 dB coupler including a transmission line. Moreover, in this system, linearity of the whole amplification device does not depend on linearity of each amplifier, and each amplifier can perform only saturated operation. Accordingly, a class B-C amplifier which has high saturated efficiency can be employed as each amplifier. High efficiency can be obtained compared with a case where an amplifier which operates as a current source is used independently.
The number of the power amplifiers which operate in a small amplitude domain decreases in this system on the operating principle, and each amplifier is operating with a saturated efficiency. Accordingly, an output modulation signal amplified with high efficiency and a back off is obtained as a result.
In the related technologies of patent document 1 and patent document 2 shown in FIG. 10 and FIG. 11, the precision in an amplitude direction is decided by the number of the amplifiers, that is, the number of bits of the AD converter.
However, a signal with large PAPR is used in wireless communications such as a mobile phone, a wireless LAN, and terrestrial digital broadcasting in recent years. Therefore, the large number of bits is needed in order to obtain the desired SN ratio. For example, a digital signal of 12-14 bits is used for a signal from a baseband in a base station of a mobile phone. In order to realize the same SN (Signal to Noise) ratio in the related technology described in patent documents 1 and 2, power amplifiers of the same number (twelve to fourteen) need to be installed.
In contrast, a related technology which reduced the number of the power amplifiers is disclosed in non-patent documents 1 and 2. In these technologies, delta-sigma modulation is applied to a signal (an output of an Envelope Detector) which detected an amplitude component of an input modulation signal, and the result thereof is multiplied by a phase modulation signal (an output of Limiter and TimeDelay) of an input modulation signal. The output signal is inputted to a switching amplifier (1 bit amplifier), and output the RF output via a filter. In this configuration, the class D switching amplifier which performs switching operation is only one in a power amplifier.